Guided Exploration of two FPGA-based CPU Designs
class #2, June 26, 1999: QS5 Baby RISC

Architecture and Implementation

The Verilog and Forth source code can be found here.

During the first half of this class I plan to lead you through the QS5 cycle-by-cycle, looking at the Verilog code and its relationship to the individual instructions. The qs5paths.pdf file will be the basis for this exploration, so look at it if you can.

During the second half, I'd like to start from the other side and look at how the qs5 implements the Forth virtual machine. For this, looking at the test.f file will be useful.

Some of you will be working on getting the metacompiler and qasm assembler to work on your system--please share what you did. Others will have found a workable Verilog simulator and gotten the simulator's output (qs5_hdl.out) to match the 'golden' output provided. (Because of differences between vendors, the first few lines may not match exactly--that's ok!) Still others may need some help--PLEASE ask for it!

Then in July we might be ready to start in on the 'twostack' architecture.


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John Rible email: inquiry@sandpipers.com

Updated 6/15/99 ()