Guided Exploration of two FPGA-based CPU Designs
led by John Rible, SandPiper Technology

a frame from Jeff's video


I’d like to see more people experimenting/playing with small CPU designs, extending our knowledge of what is possible with ‘minimal’ amounts of hardware and software. Toward that end, I propose to lead an exploration of two CPUs, my QS5 Baby-RISC and a 16-bit implementation of Chuck Moore’s dual-stack architecture. Both of these CPUs can be implemented in a small, low-cost, FPGA connected to a PC’s parallel port. Of course, the software running on them will be Forth. We can meet monthly during the SVFIG morning session for as long as you are interested, with lots of work and electronic communication in between.

The designs for the two CPUs are in the HDL (hardware design language) Verilog, and the Xilinx design software will translate this to gates without having to write schematics (logic synthesis). I strongly recommend the book HDL Chip Design as a Rosetta stone, as it shows the Verilog and VHDL (the other major HDL) code for many common components along with the synthesized logic.

a frame from Jeff's video

The tools for the chip's software are in Forth, and will run under either Win32Forth or SwiftForth. The QS5 has a target assembler, dissasembler, metacompiler, and a few tools, plus the Forth source of e4th. I’m not sure what tools Dr. Ting has for the P16, but in the best Forth tradition, we’ll develop what we need as we go.

Prentice-Hall has published a Xilinx FPGA lab book and win95/NT software which includes a coupon for an XESS FPGA board. Adding the cost of a power supply, you can be doing experiments for less than $250. The MAJOR drawback to the Xilinx software is that it wants 350MB of your hard disk to install, although it ONLY leaves 150MB there! MAJOR BLOATWARE! Other limitations are the lack of human support from Xilinx (they get no royalties from Prentice Hall!) and the limited number of installs you can do (it’s a node-locked license with automatic registration through their web page, limited to 3 different drive IDs-don't reformat your drive).

Getting started

Before the May 22nd first class meeting: purchase, install, and get familiar with the Xilinx software and XESS board (by working through some of the lab examples) and install one of the Forth systems. Send me an email when you're ready to go, and I'll add you to a class email list so that we can do this collaboratively.

Jeff Fox has offered to provide a live connection for people who can't make it to the Silicon Valley FIG meetings. He's planning on videotaping the presentations, displaying occasional snapshots in one frame, while running a chat-room connection in another.

Required materials

Xilinx Student Edition 1.5, 1999, Prentice-Hall, ISBN 0-13-020586-9 ( Computer Literacy, $87+tax).

XESS XS40-005XL Board, $109 includes shipping, or $169 for the XS40-010XL, from XESS using the coupon in Xilinx Student Edition 1.5.

Win32Forth, free on the FIG page or SwiftForth, about $400 from Forth, Inc.

These all run on a PC under Windows 95 or NT, and want 64MB of RAM (need 32MB) and LOTS of disk space.

Highly Recommended

HDL Chip Design, Douglas J. Smith, 1998, Doone Publications, ISBN 0-9651934-3-8 ( Computer Literacy, $65+tax).

A Verilog simulator that can handle the 1200 lines of code in the cpu and test fixture files. There are some demo/low-cost(?) ones listed here. (The Xilinx package only supports functional, not behavioral/rtl, simulation, which makes testing the cpu too tedious to consider.)

Also available

Jeff Fox is making video tapes of these classes available through his UltraTechnology web site.

SandPiper logo look at source files
ahead to first class

John Rible email:

Updated 6/15/99 ()