Guided Exploration of two FPGA-based CPU Designs
Files information

The files I've been using in my QuickLogic-based environment will have to be modified for this class. I'm publishing the current versions so that those who know this stuff can get something running (simulating) with a minimum of fuss, and then help the rest of the group get it working in the Xilinx/XESS environment. The directory tree is complete for the class, but some files (e4th and twostack) aren't ready yet.            - (102KB) hierarchical collection of all the files below

cpuclass/    = root

   babyrisc/      = qs5-specific directory tree

      forth/         = forth source (your Forth's 'current directory')
         makeqasm.f     - 'include-file' that builds the assembler
                           usage: INCLUDE MAKEQASM.F / leaves assembler in memory
         maketest.f     - 'include-file' that builds the test image
                           usage: INCLUDE MAKETEST.F / writes '..\test\test.mem' file
         qasm.f         - assembler/disassembler source code
         test.f         - qs5 test source code

      test/          = test directory (the simulator's 'current directory')
         qs5_gold.out   - 'golden' simulator output file to test yours against
         qs5_hdl.spj    -  SilosIII script file for behavioral simulation
                              (it has the net names for the waveform viewer)
         qs5_hdl.v      -  SilosIII include file for behavioral simulation
         qs5_net.spj    -  SilosIII script file for functional simulation
         qs5_net.v      -  SilosIII include file for functional simulation
         qs5_par.spj    -  SilosIII script file for timing simulation
         qs5_par.v      -  SilosIII include file for timing simulation
         test.chr       -  Verilog 'readmemh' file with simulated keyboard entries
                              (built by hand)
         test.mem       -  Verilog 'readmemb' file with binary memory image of the
                              test program (built by maketest.f)

      verilog/       = verilog source files
         qs5_mix.v      - behavioral/rtl source code for the qs5    - test-fixture source for my 8-bit QuickLogic board

   docs/          = various helpful documents
      qs5paths.pdf      - (85KB) The datapath block diagram showing the active busses during
                              each clock cycle

   forth/         = non-specific forth source
      meta.f            - source code for my target compiler
      tools.f           - source code for some target-image tools (some chip-specific)

   twostack/      = 'two-stack'specific directory tree

      forth/         = forth source (your Forth's 'current directory')

      test/          = test directory (the simulator's 'current directory')

      verilog/       = verilog source files

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John Rible email:

Updated 6/15/99 ()